The present invention relates to bus scaling in multibus, multiprocessor environments. In particular, the present invention relates to scaling multiple or redundant busses in multiprocessor environments under various conditions.
Many computer systems have taken advantage of the proliferation of high speed peripherals and corresponding demand for high capacity throughput by incorporating a dual bus or multibus architecture in a multiprocessor environment. Along with bus redundancy, processor and device redundancy allow greater levels of throughput to be achieved along with other advantages known to those skilled in the art.
When devices in multibus environment fail however, it is possible that an entire bus may be rendered unstable and thus unusable, and operations of the computer system may need to be shut down until defective devices can be replaced and the associated busses can be reactivated. In high end servers, for example, a huge number of tasks may be serviced by a single server making down time undesirable. It is often the case that servers supporting critical applications, particularly in the area of financial transactions, are intolerant to any server down time. Features such as hot pluggability of peripherals and the like have been developed to ensure that critical operations are maintained without bringing the system down when devices such as communications cards, disk drives and the like, are installed or removed. However with processors and other critical devices, serious problems arise when contemplating their installation or replacement without inhibiting system operation.
In an advance multibus multiprocessor environment, for example, tag RAMs coupled in most cases to each bus are used to provide cache coherency by storing cache address tags as is known and widely practiced in the art. However, when tag RAMs experience a failure such as a parity error, there is typically no error correction incorporated into the tag RAM. The only recourse available, when even a single tag RAM is found to contain errors, is to bring the system down. The system remains inoperable until the defective memory is replaced.
In addition it is possible that in a multiprocessor environment, a processor or its power supply, for example, may be defective. A defective processor may be unstable and may also require that the entire system be shut down since a failed processor cannot typically be reliably isolated from its bus. It may be possible for a failed processor in a particular failure mode to be tristated from its bus. However, it is not proven that, especially in the case of power loss, processor tristating can be guaranteed. Moreover, the probability is high that the failure mode involves the processor, for example, having undefined output or loss of power such that the bus will be affected. Such a failure mode may pull the bus voltage down or inundate the bus with a continuous stream of bad data. Reliable operations may not be guaranteed until the processor or power module is replaced and in most cases no system operation at all is possible.
While the above problems relate to the effect of device failure, including processor failure, on bus and system operation in a multibus, multiprocessor computer system, there are related problems associated with populating sockets or slots allocated for additional devices and processors while the system is in operation. Hot pluggability is a feature commonly required of peripherals but is generally reserved for slots which accept a circuit card. Hot pluggability of peripheral cards is possible due in part to the ability of the card to mechanically mate in a precise and predictable fashion allowing contacts to be made in an acceptable sequence for the application of power, ground, clock signals, and the like and to promote a known operational state to be attained by the peripheral when plugging is complete. Since processors, memory devices, and the like are not only more complicated than peripherals, but are often more sensitive to electrical anomalies such as static discharge, hot plugging such devices carries more risks and has not been possible. Moreover, the speed and complexity of a processor, raises the possibility that unless the processor or device is properly seated before it is prepared for operation, its state could be rendered indeterminate due to the smallest electrical irregularity or perturbation even if of a transient nature.
It would be desirable therefore for an apparatus and method for allowing the removal, installation, or replacement of a processor or device in a multi-bus, multiprocessor system. It would further be desirable for such a apparatus and method which would allow such removal, replacement, or installation while allowing operation of the computer system to be continued.
The present invention overcomes the above identified problems as well as other shortcomings and deficiencies of existing technologies by providing a apparatus and method for down scaling performance of a multibus multiprocessor system by disabling one or more busses in a multibus multiprocessor system associated with one or more inoperative, disabled, or uninstalled processors, or inoperative memory device on the affected one or more busses. The present invention further overcomes the problems identified with the prior art by allowing processors and critical devices to be plugged into an operating computer system and reactivating the associated bus when devices are successfully plugged in.
In a computer system with an architecture having two or more separate busses, there may be, for example, four processors on each bus providing built-in redundancy. Tag RAMS may further provide processors in the multiprocessor environment of the present invention with enhanced cache coherency. If, for example, one or more of the exemplary four processors or one of the tag RAMs associated with one bus is inoperative or uninstalled, the present invention allows the computer system to operate in a scaled-down performance mode on the remaining bus in a two bus system or remaining busses in a multibus system.
For example, if a parity error is detected in a processor tag RAM, the computer system may reboot and, using the apparatus and method of the present invention, the defective tag RAM may be disabled upon reboot. The one or more affected busses may be disabled and the computer system may be brought back up in a single-bus operational mode. Such an apparatus and method may be applied as a general-purpose recovery method for any dual-bus or multibus system wherein a critical failure state involving a processor or memory device may be detected and the computer system may be rebooted with the bus or busses corresponding to the affected processor or device being disable and limited operations may be sustained with one bus operational.